Building the toolchain for HLS-based accelerator design. Anthony Kung, OSU STAR Lab, NSF CROSS Project.

A long-term sparse-tensor accelerator goal and a compact Transformer-block proxy workload motivate an ASIC-viable model-to-layout flow.

Specialized hardware can improve latency and energy efficiency for emerging machine-learning workloads and constrained edge deployments.

Establish an automated ASIC-viable research toolchain that preserves structural and timing intent, supports optimization, and validates manufacturability.

The original path lowered an untimed C design through Bambu HLS to Verilog RTL and an open-source ASIC flow.

Bambu-generated RTL and the open-source synthesis flow exposed structural, memory, and control incompatibilities that blocked complete ASIC synthesis.

Vivado provided a functional fallback that validated accelerator behavior and performance, but FPGA success did not establish ASIC manufacturability.

The project pivoted to SystemC, Catapult HLS, Cadence Genus, and Cadence Innovus for an ASIC-oriented methodology.

SystemC captures intent, Catapult performs high-level synthesis and RTL verification, and Cadence tools synthesize, place, route, and report timing, power, and area.

SystemC adds concurrency, communication, and timing structure to C++ so the model expresses a synthesizable accelerator architecture.

Catapult translates SystemC into Verilog RTL while scheduling operations, allocating resources, and applying timing and area constraints.

Tool-version, licensing, simulation, path, and downstream component issues complicated the commercial proof-of-concept flow.

Genus synthesizes Catapult RTL into a technology-mapped gate-level design and reports timing, power, and area.

Innovus places and routes the synthesized design, performs clock-tree and interconnect work, and checks sign-off-quality layout constraints.

Complete the Catapult-to-Genus-to-Innovus proof of concept, automate SystemC generation, and replace the proxy with representative sparse kernels.

The redesigned methodology separates algorithmic intent, HLS, synthesis, and physical design to create a practical path from model to manufacturable accelerator.

End of the original 2025 presentation.